A processor controlled communication system typically includes at least one processor (CPU), one or more memory components and one or more input/output (I/O) interfaces. Each memory component provides program and data storage while each I/O interface connects the communication system to any of a variety of data devices.
Because the processor can only communicate with one I/O interface at a time, each I/O interface is assigned a priority level to resolve simultaneous service requests from different I/O interfaces of the system. In the prior art, priority was often assigned in accordance with the slot in the system into which the I/O interface was connected. Undesirably, the priority assignment was fixed by the physical location of the I/O interface. To provide an adjustable priority assignment, some systems included straps on the backplane or switches on each I/O interface card. During the operation of the system, it is often necessary to dynamically change the priority of one or more I/O interfaces in response to internal or external stimuli. In addition, straps and switches also complicate the installation and maintenance of the system. The problem then is to provide a system with a capability to dynamically adjust the priorities of I/O interfaces.